3GPP Compliant Polar Encoding/Decoding Chain

Xilinx FPGA IP core



Our patent-pending polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimise the amount of extra work needed. The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.

In version 2.0, we will implement further algorithmic optimisation and pipelining, which we expect to significantly improve the latency, throughput and hardware efficiency. 

Please contact us using the details below for updates and for information on our polar encoding and decoding IP for the other 3GPP New Radio channels.


  • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. No limitations on uncoded or encoded block size to ensure future compatibility.
  • Implements the entire polar encoding and decoding chain in 3GPP TS38.212, including segmentation; channel (de)interleaving; rate (de)matching; sub-block (de)interleaving; pattern generation; CRC6, CRC11 and CRC24C calculation; CRC early stopping (for PDCCH blind decoding); CRC (de)interleaving; RNTI (de)scrambling.
  • High error correction performance from PC/CRC-aided core. 
  • Tightly integrates the components in the chain to reduce area usage and latency.
  • Simple interface, quick to integrate – all parameters are internally calculated – only the number of uncoded bits (A) and encoded bits (E) needs to be input alongside the bits or LLRs.


This block diagram shows all the components required in the decoder for full 3GPP compliance. Our encoder also implements all the corresponding components for encoding.



Encoding chain

Decoding chain

IP Information


Design files

RTL source files or FPGA netlist

Language (RTL)



AXI4-Stream for input and output

Hardware resource

Contact AccelerComm


Datasheet, integration guide, example testbench with .tcl scripts





FPGA vendor


Devices verified


Memory files (RAM/ROM)

Vendor specific models with

.mif or .hex data files (for ROM) 





Language (Testbench)


Testbench and design example

DPI-based, bit accurate, with throughput and latency measurements.

Models provided

Bit-accurate static or dynamic library for Windows and Linux;

Clock cycle models for latency and throughput




AccelerComm is a semiconductor IP-core company that provides patent-pending channel coding solutions. Our team has over 50 person-years of channel coding and IP experience, from developing and optimising algorithms through to their implementation and delivery in FPGA and ASIC architectures. With more than 100 published IEEE papers and numerous citations for our work in 3GPP RAN1, we are having a significant impact on the mobile communications world. 

You can find out more about us at www.accelercomm.com.


Robert Barnes


VP Sales and Marketing

[email protected]


Prof Rob Maunder



[email protected]


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