Polar

product-icon-polar

3GPP compliant encoding & decoding chain

AccelerComm polar encoding and decoding IP for the 3GPP NR uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed. The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.

Features

  • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
  • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
  • High error correction performance from Polar PC/CRC-aided decoder core
  • Simple interface, quick to integrate. Only the number of uncoded bits (A) and encoded bits (E) needs to be input alongside the bits or LLRs
  • Tightly integrates the components in the chain to reduce area usage and latency
  • FPGA support Optimized for ASIC process
  • Matlab and C Models available
  • Configurable parameters for power and performance optimization
  • Scalable design with configurable list size
  • Standard AXI interfaces

 

Functional specifics

Encoder Decoder
CRC encoding PC and CRC decoding
Zero padding Sub block de-interleaving
CRC24C attachment Filler bits insertion/removal
CRC scrambling and interleaving Rate dematching
Frozen bit insertion Channel de-interleaver
Sub block interleaving  
Rate matching  

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If you’d like to discuss how our physical layer solutions can help your business thrive today and into the future, please get in touch.

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