3GPP Compliant Encoding/Decoding Chain

Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimise the amount of extra work needed. The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.

In version 2.0, we have implemented further algorithmic optimisation and pipelining, which significantly improve the latency, throughput and hardware efficiency. 

Please contact us using the contact form for updates and for information on our polar encoding and decoding IP for the other 3GPP New Radio channels.

 

Features

  • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. No limitations on uncoded or encoded block size.
  • Implements the entire polar encoding and decoding chain in 3GPP TS38.212, including: segmentation (uplink); channel (de)interleaving; rate (de)matching; sub-block (de)interleaving; pattern generation; CRC6, CRC11 and CRC24 calculation; CRC early stopping (for PDCCH blind decoding); CRC (de)interleaving; RNTI (de)scrambling
  • High error correction performance from PC/CRC-aided core. 
  • Tightly integrates the components in the chain to reduce area usage and latency
  • Simple interface, quick to integrate – all parameters are internally calculated – only the number of uncoded bits (A) and encoded bits (E) needs to be input alongside the bits or LLRs.

 

Product

Encoding chain; decoding chain

IP Information

 

Design files

RTL source files or FPGA netlist

Language (RTL)

SystemVerilog

Interfaces

AXI4-Stream for input and output

 

 

FPGA

 

FPGA vendors

IntelFPGA, Xilinx, Achronix

Devices verified

Kintex 7, Virtex 7, Ultrascale(+), Arria 10, Stratix(V/10)

Memory files (RAM/ROM)

.mif or .hex (for ROM) with vendor specific models

ASIC

 

Nodes verified

14nm, 28nm

Tools used

Synopsys DC, Spyglass

RAM/ROM instantiation

Easy to use template to add user-specific memory models

Verification

 

Language (Testbench)

SystemVerilog

Testbench and design example

DPI-based, bit accurate, with throughput and latency measurements.

Models provided

Bit-accurate static or dynamic library for Windows and Linux;

Clock cycle models for latency and throughput

Also available

AVX-512 optimised decoder

 

AccelerComm is a semiconductor IP-core company that provides patented channel coding solutions. Our team has over 50 person-years of channel coding and IP experience, from developing and optimising algorithms through to their implementation and delivery in FPGA and ASIC architectures. With more than 100 published IEEE papers and numerous citations for our work in 3GPP RAN1, we are having a significant impact on the mobile communications world. You can find out more about us at www.accelercomm.com.

As a consequence of this,  we have a unique patented architecture, which elegantly solves the biggest implementation challenge in polar code and hence significantly reduces resource and memory usage compared to the previous state-of-the-art.  Our approach also enables higher degrees of parallel processing than has previously been demonstrated. In combination, these advantages grant superior hardware efficiency and reduce throughput latency.

All our polar IP is available for hardware implementation in FPGA and ASIC or in SW for Intel's Skylake scalable processors

Polar Encoder

Contact us for the latest on Achronix support for AccelerComm Polar encoder on their of Speedster® FPGAs as well as Speedcore™ embedded FPGAs (eFPGAs)

Click here to receive the latest data sheet for implementation in Altera FPGA

Click here to receive the latest data sheet for implementation in Xilinx FPGA

Click here to receive the latest on the implementation in TSMC 28nm ASIC process

Click here to receive the latest on the SW implementation

Polar Decoder

Contact us for the latest on Achronix support for AccelerComm Polar decoder on their of Speedster® FPGAs as well as Speedcore™ embedded FPGAs (eFPGAs)

Click here to receive the latest data sheet for implementation in Altera FPGA

Click here to receive the latest data sheet for implementation in Xilinx FPGA

Click here to receive the latest on the implementation in TSMC 28nm ASIC process

Click here to receive the latest on the SW implementation

 

Organisations we work with