AccelerComm was present at the 3GPP TSG RAN WG1 meeting in November 2016 in Reno, when the decision was taken to include polar codes in the control channel of eMBB for 5G NR and we have been an active member of the on-going discussions. 

As a consequence of this,  we have a unique patent-pending architecture, which elegantly solves the biggest implementation challenge in polar code and hence significantly reduces resource and memory usage compared to the previous state-of-the-art.  Our approach also enables higher degrees of parallel processing than have previously been demonstrated. In combination, these advantages grant superior hardware efficiency and reduce throughput latency.

All our polar IP is available for hardware implementation in FPGA and ASIC or in SW for Intel's Skylake scalable processors

Polar Encoder

Contact us for the latest on Achronix support for AccelerComm Polar encoder on their of Speedster® FPGAs as well as Speedcore™ embedded FPGAs (eFPGAs)

Click here to receive the latest data sheet for implementation in Altera FPGA

Click here to receive the latest data sheet for implementation in Xilinx FPGA

Click here to receive the latest on the implementation in TSMC 28nm ASIC process

Click here to receive the latest on the SW implementation

Polar Decoder

Contact us for the latest on Achronix support for AccelerComm Polar decoder on their of Speedster® FPGAs as well as Speedcore™ embedded FPGAs (eFPGAs)

Click here to receive the latest data sheet for implementation in Altera FPGA

Click here to receive the latest data sheet for implementation in Xilinx FPGA

Click here to receive the latest on the implementation in TSMC 28nm ASIC process

Click here to receive the latest on the SW implementation

Organisations we work with