3GPP compliant coding and modulation for Physical Shared Channels
AccelerComm’s latest products, PDSCH Encoder and PUSCH Decoder, provide Forward Error Correction (FEC) encoding and decoding capabilities along with the complete Quadrature Amplitude Modulation (QAM) modulation and demodulation functionality for downlink and uplink data processing in a gNB/base station.
- They are implemented as per the latest 3GPP specifications and are compliant with TS 38.211 and 38.212.
- The new QAM modulator/demodulator functionality complements the existing high performance AccelerComm LDPC and Polar encoder/decoder solutions.
- Like all AccelerComm IP the modulator/demodulator is configurable to several different parallelisms to optimise the area/power/performance of each integration.
These are high-level block diagrams of the various functions within these PxSCH encoder and decoder products.
- The PDSCH Encoder and PUSCH Decoder products simplify the creation of high performance 5G NR implementations.
- PDSCH Encoder features the new QAM mapper and Scrambler functionality. These are integrated with LDPC encoder chain and transport block chain components.
- PUSCH Decoder features the new QAM demapper, descrambler and demultiplexer.
- These new functions are integrated with LDPC and Polar decoders, code block chain and transport block chain components.
- PUSCH Decoder also allows for Uplink Control information (UCI) to be multiplexed onto the PUSCH. The complicated implementation of UCI over PUSCH is part of this AccelerComm product and helps with simpler integration on target devices. The tight AccelerComm integration leads to improved multiplexed UCI BLER for critical HARQ-ACK messages.
- Complete implementation of the relevant 3GPP standard
- Improved BLER for UCI control data
- Pre integrated with AccelerComm LDPC and Polar encoders/decoders chains and inherits all the benefits from these
- Single control interface
- Supported across FPGA and ASIC platforms
- Highly configurable for a wide range of base station (gNB) applications
- Configurable to support maximum throughputs and minimum timing requirements for all numerologies
- Very low latency – meets strictest requirements for uRLLC
- Efficient design – saves device area
- Easy to integrate using industry standard AXI interfaces
The figures below show the functionality within the products, implemented as per the referenced 3GPP specifications.
For datasheets for our PxSCH product, including bloc diagrams, performance graphs and other KPI comparisons...contact us
For more about our configurable LDPC encoder and decoder with multiple algorithm support for optimal BLER performance...VIEW PRODUCT
For more about our Polar architecture, designed to provide excellent error correction performance within the minimum area...VIEW PRODUCT
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