3GPP compliant encoding & decoding chain

Video 8 - Furure Proofing base stations for 5G v2
Rob Maunder, CTO - LDPC channel code for 5G new radio

Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.

The LDPC core uses novel layer belief propagation schedules with early termination, in order to achieve compromise-free error correction performance with high hardware efficiency.

The diagrams below shows the various functions performed by the AccelerComm IP for Layer 1 (Physical Layer) of NR radio interface. The focus is on data channels coding with the first diagram showing blocks for LDPC encoding of physical shared channels (PDSCH/PUSCH) referred to by AccelerComm product number LD550 and LE550. The second diagram represents the LDPC decoding blocks for the same physical shared channels on the receive side. All products include Transport Block processing and HARQ management in hardware.

Features

  • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
  • Implements the entire LDPC encoding and decoding chain in 3GPP TS38.212
  • High error correction performance from LDPC decoder core
  • Tightly integrates the components in the chain to reduce area usage and latency
  • Simple interface, quick to integrate – all parameters are internally calculated
  • FPGA support for Xilinx, Intel and Achronix
  • Optimized for ASIC process
  • Optimized software solution on Intel Architecture and AVX512 acceleration
  • Matlab and C Models available
  • Configurable parameters for power & performance optimization
  • Scalable design
  • Standard AXI interfaces

Functional specifics

Encoder Decoder
Transport Block CRC encoding Transport Block CRC decoding
Code block segmentation Code block de-segmentation
CRC encoding CRC decoding
LDPC encoding
(basegraph 1 and 2, all Z-values)
LDPC decoding
(basegraph 1 and 2,  all Z-values)
Rate matching (incl. repetition) HARQ combining
Bit-level interleaver Filler bits insertion/removal
Filler bits insertion/removal Inverse Rate matching (incl. repetition)
Code block concatenation Bit-level de-interleaver
  Soft-output interface (optional)
  Re-encoded output stream (optional)
  Code block de-concatenation

 

Applications

The LDPC encoding and decoding chains are the building blocks that furthers usage in a variety of applications. Our flexible IP can be used in a wide range of applications ranging from ASICs for dedicated implementations through lookaside accelerators for cloud RAN and software implementations.

Lookaside Hardware Acceleration

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Software Acceleration for FlexRan

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SD-FEC Compliant Chain

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Product Codes

 

Code Description Delivery Type
LD350

A pre & post processing wrapper that completes the 5G NR 3GPP compliant chain when using a Xilinx SD-FEC LDPC Decoder Core.

FPGA Netlist (Xilinx Only)

LE350

A pre & post processing wrapper that completes the 5G NR 3GPP compliant chain when using a Xilinx SD-FEC LDPC Encoder Core.

FPGA Netlist (Xilinx Only)

LD500

 

LDPC Decode core only with optimized algorithms for ultimate BLER performance ideal for Satellite applications.

Encrypted RTL or FPGA Netlist

LE500

LDPC Encode core only optimized for performance and low power ideal for Satellite applications.

Encrypted RTL or FPGA Netlist

LD550

Complete LDPC Decode 5G NR 3GPP chain. See LDPC decoder chain diagram

Encrypted RTL or FPGA Netlist

LE550

Complete LDPC Encode 5G NR 3GPP chain. See LDPC encoder chain diagram

Encrypted RTL or FPGA Netlist

LD600

Optimized decoder core only for Intel Architecture (IA) and AVX512 co-processor.

Software binary for IA

LD850

To enable higher throughput and reduce CPU load. Transport block processing can be added with deconcatenation and TB CRC.

Encrypted RTL or FPGA Netlist

LE850

To enable higher throughput and reduce CPU load. Transport block processing can be added with concatenation and segmentation.

Encrypted RTL or FPGA Netlist

T1 L1 Acceleration

A Complete L1 acceleration system using ORAN API’s to offload LDPC processing from L1 stack. Simple integration and high performance (e.g. 16Gbps decode with PCI Gen3 x 16).

Encypted Netlist & Software installer for ORAN api (server side)

Technical resources

Our technical resources are freely available for anyone to download. Research and innovation form an integral part of our business and we want to share this with you.

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Datasheets

Detailed specification sheets for our LDPC product, including block diagrams, performance graphs and comparison tables.

View Datasheets
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Whitepapers

Research, technical leadership and tutorial papers from our CTO on the latest factors influencing the future of LDPC standards.

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Software

Open source software models and evaluation code for encoder and decoder simulations for our LDPC product.

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AccelerComm intro presentation

Delivering 5G communications

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LDPC product overview

5G NR LDPC Product Overview

Key features and benefits of our LDPC product suite for 5G New Radio Applications.

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Latest news & media

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AccelerComm's product roadmap to complete PHY solutions

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AccelerComm joins DARPA Toolbox initiative for advanced communications research projects

AccelerComm joins DARPA Toolbox initiative for advanced communications research projects

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Contact us

We are transforming the next generations of wireless communications with innovative, world-leading IP that delivers ultra-high performance and error resilient signal processing. Let’s connect to discuss how our channel coding solutions can help your business thrive today and into the future.

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