3GPP compliant encoding & decoding chain
Rob Maunder, CTO - LDPC channel code for 5G new radio
Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.
The LDPC core uses novel layer belief propagation schedules with early termination, in order to achieve compromise-free error correction performance with high hardware efficiency.
The diagrams below shows the various functions performed by the AccelerComm IP for Layer 1 (Physical Layer) of NR radio interface. The focus is on data channels coding with the first diagram showing blocks for LDPC encoding of physical shared channels (PDSCH/PUSCH). The second diagram represents the LDPC decoding blocks for the same physical shared channels on the receive side. All products include Transport Block processing and HARQ management in hardware.
- Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
- Implements the entire LDPC encoding and decoding chain in 3GPP TS38.212
- High error correction performance from LDPC decoder core
- Tightly integrates the components in the chain to reduce area usage and latency
- Simple interface, quick to integrate – all parameters are internally calculated
- FPGA support for Xilinx, Intel and Achronix
- Optimized for ASIC process
- Optimized software solution on Intel Architecture and AVX512 acceleration
- Matlab and C Models available
- Configurable parameters for power & performance optimization
- Scalable design
- Standard AXI interfaces
|Transport Block CRC encoding||Transport Block CRC decoding|
|Code block segmentation||Code block de-segmentation|
|CRC encoding||CRC decoding|
(basegraph 1 and 2, all Z-values)
(basegraph 1 and 2, all Z-values)
|Rate matching (incl. repetition)||HARQ combining|
|Bit-level interleaver||Filler bits insertion/removal|
|Filler bits insertion/removal||Inverse Rate matching (incl. repetition)|
|Code block concatenation||Bit-level de-interleaver|
|Soft-output interface (optional)|
|Re-encoded output stream (optional)|
|Code block de-concatenation|
The LDPC encoding and decoding chains are the building blocks that furthers usage in a variety of applications. Our flexible IP can be used in a wide range of applications ranging from ASICs for dedicated implementations through lookaside accelerators for cloud RAN and software implementations.
Our technical resources are freely available for anyone to download. Research and innovation form an integral part of our business and we want to share this with you.
Detailed specification sheets for our LDPC product, including block diagrams, performance graphs and comparison tables.View Datasheets
Research, technical leadership and tutorial papers from our CTO on the latest factors influencing the future of LDPC standards.View Whitepapers
Open source software models and evaluation code for encoder and decoder simulations for our LDPC product.Access Software
We are transforming the next generations of wireless communications with innovative, world-leading IP that delivers ultra-high performance and error resilient signal processing. Let’s connect to discuss how our channel coding solutions can help your business thrive today and into the future.Get in touch