PUSCH Equalizer

Advanced 3GPP compliant equalization, double uplink performance and spectral efficiency with this 5G NR Uplink Physical Shared Channel solution

AccelerComm’s PUSCH (Physical Uplink Shared Channel) Equalizer IP product offers a complete high-performance 3GPP compliant PUSCH channel for a gNB, bringing on average 29% savings in infrastructure power and equipment cost for typical private networks and $193M increase in Net Present Value for typical Fixed-Wireless Access networks.

MIMO equalization

MIMO equalization is fundamental in 5G NR to tackle co-channel interference imposed by multiple transmissions in the time, frequency and space domains, to achieve ever higher spectral efficiency and reduce cost per bit for 5G applications in sub 6GHz and mmWave. To hit a ‘sweet spot’ between computational complexity and spectral efficiency, many challenges must be overcome. AccelerComm has introduced advanced 5G NR MIMO equalization techniques based on state-of-the-art algorithms such as MMSE-IRC, to enable higher spectral efficiencies at both low and high SNRs. Delivering a 3dB improvement in uplink receive sensitivity for a deployed gNodeB solution, these techniques can be deployed in 5G small cell, macro cell and satellite applications.

Integrating and validating the whole set of signal processing tasks of the Physical Uplink Shared Channel (PUSCH) channel requires a significant investment in engineering resource. Trusted by Tier-1 technology companies and leading semiconductor companies with our 5G NR IP, AccelerComm has built up a strong product portfolio and expertise in the field of the L1 physical layer. With LDPC, Polar, PDSCH Encoder, PUSCH Decoder and now PUSCH equalizer (MIMO equalization), AccelerComm’s latest IP product offers benefits of UCI over PUSCH and improved throughput and dB gain for the PUSCH channel, while greatly reducing the risks and providing market-leading solutions and faster time to market for FPGA and ASIC 5G platforms.

Functionality

The AccelerComm PUSCH Equaliser product provides complete decoding functionality along with channel equalisation for uplink processing in a gNB covering the relevant sections of TS 38.211 and 38.212. 

The PUSCH Equaliser features the new channel equaliser designed by our research team for best performance vs hardware complexity trade-off. This new function is integrated with our market leading PUSCH Decoder IP product which includes QAM demapper, descrambler, demultiplexer, LDPC decoder, Polar decoder and HARQ buffering components. 

This product is capable of equalising MIMO layers and performing interference removal, noise reduction and channel coding to recover the message as part of the High PHY processing. A single instance can support max 4 spatial streams (logical gNodeB receive antenna ports) and max 4 uplink MIMO layers for single-user MIMO, and multiple instances of the IP can be used to support multi-user massive MIMO.

Performance

5G NR targets throughputs up to 20Gbps with sub 1ms latencies, across a wide range of radio conditions. However, the standard is flexible, and many applications require different levels of performance targets. Like all AccelerComm IP, the PUSCH Equaliser is configurable to several different parallelisms to optimise the area / power / performance of each solution.

Many cloud RAN architectures make use of the concept of lookaside acceleration for LDPC, typically implemented on a plug-in card over a PCI Express bus. Throughput between different signal processing tasks in the physical layer can be then challenging,  especially in a software system using hardware acceleration. Traffic protocols, connectivity IPs and physical interfaces often impose huge overheads and bottlenecks on the throughput, further hindering the performance of the entire physical layer. With AccelerComm PUSCH Equaliser, not only does it offload more than the LDPC lookaside function to offer higher bit/s/Hz throughput efficiency for the High PHY, but also reduces CPU load and power consumption while significantly reducing the PCIe bandwidth. To support this advanced lookaside architecture  AccelerComm are working with ORAN working group to extend the AAL interface for a standards based approach. 

Improved Multiplexed UCI BLER

When sending short ACK messages over the UCI channel multiplexed over PUSCH, the 3GPP standard specifies the use of placeholder filler bits which maximise the chances of correctly decoding these critical messages. As the AccelerComm QAM demapper is integrated with the demultiplexer, it can identify the QAM symbols that represent the ACK bits and process them, accordingly, ensuring the lowest possible error rate.

Improved Throughput and dB Gain

IQ symbols received from the fronthaul are inevitably impaired by the interference and noise introduced. With a novel patent-pending MIMO equalisation algorithm and hardware architecture, the AccelerComm channel equaliser together with coding can offer 3 to 10 dB gain in the PUSCH Equaliser.

The diagram below shows an example of the 3GPP 5G NR PUSCH using 4 transmission MIMO layers, 4 UE transmit antenna ports, 4 gNodeB receive antenna ports, 256QAM modulation, low code rate for numerology 0 with two interferers. The performance plot quantifies throughput vs SINR, where 100% throughput represents HARQ processes succeeding during the first transmission, with no need for any HARQ retransmissions. The simulation measures and compares the throughput achieved by two sets of receiver components - the first adopts the AccelerComm equaliser, QAM demapper and LDPC decoder components, while the benchmark adopts the corresponding components from an industry-standard toolkit. Up to 5 dB gain can be observed in the low SINR range, showcasing the performance benefit of AccelerComm PUSCH Equaliser.

Complete Integration

The new equaliser component is available in a complete integrated IP package with AccelerComm’s high performance QAM demapper, LDPC and Polar decoders. This integration simplifies development, for example the Polar and LDPC decoder and demodulator require several control parameters for each transport block sent over the PUSCH, the integrated IP block brings all the relevant information together into a single control and status memory-mapped interface.