Many cloud RAN architectures, such as Intel’s FlexRAN and the Open RAN Alliance reference architecture make use of the concept of lookaside acceleration for LDPC. Typically implemented on a plug in card over a PCI Express bus, an FPGA or ASIC will use our IP to offload the LDPC processing from the host CPU. A typical FPGA can provide the LDPC decode capacity of over 100 Intel® Xeon® CPU cores and therefore provides significant system acceleration, leading to approximately 30% CAPEX and OPEX savings from cloud RAN deployments.

DPDK / BBDEV support

Data Plane Development Kit is a widely adopted standard consisting of libraries to accelerate packet processing workloads. Within DPDK the Wireless Baseband Library (BBDEV) is being adopted as a standard for lookaside hardware acceleration of LDPC workloads, currently under consideration at ORAN working group 6.

Achieving the throughputs required for a cloud RAN solutions presents a significant challenge and we have developed an integrated high performance solution of the BBDEV API with our LDPC IP that achieves throughputs close to 90% of the theoretical capacity of the hardware interface.

BBDEV Interface

More about AccelerComm's BBDEV interface

AccelerComm’s BBDEV interface enables our high performance 5G NR LDPC encoding and decoding IP solutions to be rapidly and efficiently used as hardware accelerators in industry standard servers...

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Xilinx T1 Telco Accelerator card

Xilinx T1 Telco card

A multi-function small form factor PCIe card that AccelerComm integrated a BBDEV/DPDK L1 offload for the LDPC processing in 5G NR.

The card uses a single slot PCIe interface and is built around Xilinx Zynq Ultrascale + MPSoC & RFSoc. With two 25G SFP28 and x16 PCIe interfaces bifurcated into two x8 interfaces, this Board is dual slot FHHL (full-height, half-length) form factor.

 

T1 features

  • Xilinx ZU21DR RFSoC for 5G baseband processing offload 
  • Xilinx MPSOC ZU19EG for 5G O-RAN fronthaul termination
  • x64 bit 4GB DDR4 Memory interfaced to PL
  • x32 bit 2GB DDR4 Memory interfaced to PS
  • Two SFP28 cages for 25G
  • x16 PCIe interface bifurcated to two x8 interfaces to the host device through PCIe edge finger connector
  • x16 standard NIC card form factor (112mm x 168mm)
  • JTAG Connectors for Debugging

AccelerComm design on the T1

An L1 offload commercially deployable combination of:

  • BBDEV/DPDK standard APIs 
  • Xilinx QDMA driver for PCIe interface
  • FPGA netlist, including: 
    • QDMA channel optimization 
    • Interface logic 
    • HARQ management 
    • Complete 3GPP compliant code block processing with integrated SD-FEC
    • Configurable SD-FEC combinations supported

 

 

  • This system can easily interface to compliant 5G L1 software stack and associated test environments
  • The SmartNIC performance can be extended by further utilizing the PCI Gen3 x16 to full capacity by applying further L1 LDPC or Polar channel coding onto the ZU19EG if fronthaul acceleration is not required
  • This system has been designed to provide optimal throughput and reduced latency for real world scenarios

    READ MORE HERE

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We are transforming the next generations of wireless communications with innovative, world-leading IP that delivers ultra-high performance and error resilient signal processing. Let’s connect to discuss how our channel coding solutions can help your business thrive today and into the future.

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