Physical Channels for 5G NR

Introduction

The 5G physical channels are used to transport information over the radio channel. They have the transport channels mapped into them but they also include various physical layer data required for the maintenance and optimisation of the radio communications link between the UE and the base station such as modulation, reference signal mapping, transmit power and coding schemes. 

The physical layer channels defined in the standard for downlink are:

  • Physical Downlink Shared Channel (PDSCH)
  • Physical Downlink Control Channel (PDCCH)
  • Physical Broadcast Channel (PBCH)

The physical layer channels defined in the standard for uplink are:

  • Physical Random Access Channel (PRACH)
  • Physical Uplink Shared Channel (PUSCH)
  • Physical Uplink Control Channel (PUCCH)

AccelerComm can offer a complete integrated L1 which controls these channels however due to the wide range of supported performance points and applications for 5G, many customers may prefer to implement their own 5G modem offering key differentiation of their own. To support this activity AccelerComm licences the hardware components of the L1 channels as IP blocks for optimal power and performance based on standard interfaces and within the definition of 3GPP. Often some of these channels are controlled by software implemented in the L1 or above

 

 

PUSCH Decoder - Product icon

PUSCH Decoder

Integrating and validating the various functional blocks of the 3GPP Physical Layer consumes significant engineering resource and by providing a complete pre integrated IP solution, AccelerComm simplifies the design of a high performance gNB. For instance, a key bottleneck in the Uplink receive chain is often the very high data rate required to pass data to the LDPC decoder as LLRs. By integrating the Demodulator and LDPC Decoder and passing the data as IQ values, the AccelerComm IP offers an opportunity to reduce this bottleneck by a factor of two.

  • Implemented for 3GPP NR specifications and compliant with TS 38.211 and 38.212
  • New QAM modulator/demodulator functionality complements existing LDPC and Polar coding solutions
  • Inherits all the benefits from the existing AccelerComm LDPC, Polar encoders/decoders
  • Support for Uplink Control information (UCI) multiplexed onto the PUSCH
  • Improved BLER for UCI control data
  • Configurable to different parallelisms specific to each integration
  • Target both FPGA and ASIC implementations
Learn More About PUSCH Decoder
PDSCH Encoder - Product icon

PDSCH Encoder

Integrating and validating the various functional blocks of the 3GPP Physical Layer consumes significant engineering resource and by providing a complete pre integrated IP solution, AccelerComm simplifies the design of a high performance gNB. 

  • Implemented for 3GPP NR specifications and compliant with TS 38.211 and 38.212
  • New QAM modulator/demodulator functionality complements existing LDPC  coding solutions
  • Inherits all the benefits from the existing AccelerComm LDPC encoder
  • Configurable to different parallelisms specific to each integration
  • Optimal size, weight, area and power trade-off
  • Target both FPGA and ASIC implementations
Learn More About PDSCH Encoder
ldpc-product-icon

PUSCH Equaliser

The AccelerComm PUSCH Equaliser is targeted at improving spectral efficiency in solutions that have multiple antennas removing noise and interference. Advanced Equalisation algorithms require significant signal processing requirements and are therefore better implemented as hardware acceleration than in a general purpose CPU. This product is an extension to the AccelerComm PUSCH Decoder supporting all the same features including UCI over PUSCH but with the additional integrated Equaliser block.

  • Implemented for 3GPP NR specifications and compliant with TS 38.211 and 38.212
  • Can double spectral efficiency dependant on deployment scenario
  • Reduces cost per bit and lowers system power
  • Integrates advanced equalisation with demodulation, LDPC and polar decoding
  • Minimises time to market
  • Available for FPGA and ASIC
Learn More About PUSCH Equaliser

AccelerComm product mix

Below is a diagram showing the integrated components to the Channel IP:

Diagram by AccelerComm demonstrating a diagram showing the integrated components to the Channel IP and the comparison between PUSCH Decoder, PDSCH Encoder, and PUSCH Equaliser.

 

Testimonials

AccelerComm is providing us with Acceleration IP on our Telco Accelerator cards. They are an excellent partner. The one thing I can tell you about AccelerComm, is the high quality of their products. The out of the box experience has always been superb.

Very professionally done, very professional team, easy to work with. They’re great partners.

Raghu M Rao, Director - Wired and Wireless Communications Group AMD

AccelerComm has been a key partner in providing that flexibility in order to meet the performance requirements we need for our customers.

The relationship has been excellent. Because of the nature of our business, where we customise our solutions very specifically for our customers, there’s been a lot of engineering back and forth between ourselves and AccelerComm. And so quite often, we will need to tailor both their and our solutions to the specific requirements of a given customer.

Paul Sutton, CEO - Software Radio Systems

AccelerComm is a great partner of ours. We deliver together the IP for the FPGAs. They deliver, they support us and create for us opportunities in the market.

We love Rob. B. He is supporting us with both opportunities and technologically. So a great experience and great company to work with.

Oren Benisty, EVP Strategic Sales - Silicom