3GPP compliant encoding & decoding chain

Video 8 - Furure Proofing base stations for 5G v2

Rob Maunder, CTO - LDPC channel code for 5G new radio

Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed. The LDPC core uses novel layer belief propagation schedules with early termination, in order to achieve compromise-free error correction performance with high hardware efficiency.

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Features

  • Fully compliant with the 3GPP NR standard for PDSCH, PUSCH. Supports the full range of uncoded and encoded block sizes
  • Implements the entire LDPC encoding and decoding chain in 3GPP TS38.212
  • High error correction performance from LDPC decoder core
  • Tightly integrates the components in the chain to reduce area usage and latency
  • Simple interface, quick to integrate – all parameters are internally calculated
  • FPGA support for Xilinx
  • Optimised for ASIC process
  • Matlab and C Models available
  • Configurable parameters for power & performance optimization
  • Scalable design
  • Standard AXI interfaces

Functional specifics

Encoder Decoder
CRC encoding CRC decoding
LDPC encoding
(basegraph 1 and 2, all Z-values)
LDPC encoding
(basegraph 1 and 2,  all Z-values)
Rate matching (incl. repetition) HARQ combining
Bit-level interleaver Filler bits insertion/removal
Filler bits insertion/removal Inverse Rate matching (incl. repetition)
  Bit-level de-interleaver
  Soft-output interface (optional)
  Re-encoded output stream (optional)

Xilinx T1 Telco Accelerator card

A multi-function small form factor PCIe card that AccelerComm integrated a BBDEV/DPDK L1 offload for the LDPC processing in 5G NR. The card uses a single slot PCIe interface and is built around Xilinx Zynq Ultrascale + MPSoC & RFSoc. With two 25G SFP28 and x16 PCIe interfaces bifurcated into two x8 interfaces, this Board is dual slot FHHL (full-height, half-length) form factor.

Key features

  • Xilinx ZU21DR RFSoC for 5G baseband processing offload 
  • Xilinx MPSOC ZU19EG for 5G O-RAN fronthaul termination
  • x64 bit 4GB DDR4 Memory interfaced to PL
  • x32 bit 2GB DDR4 Memory interfaced to PS
  • Two SFP28 cages for 25G
  • x16 PCIe interface bifurcated to two x8 interfaces to the host device through PCIe edge finger connector
  • x16 standard NIC card form factor (112mm x 168mm)
  • JTAG Connectors for Debugging

Xilinx T1 Telco card

 

AccelerComm Design on T1

An L1 offload commercially deployable combination of:

  • BBDEV/DPDK standard APIs 
  • Xilinx QDMA driver for PCIe interface
  • FPGA netlist, including: 
    • QDMA channel optimization 
    • Interface logic 
    • HARQ management 
    • Complete 3GPP compliant code block processing with integrated SD-FEC
    • Configurable SD-FEC combinations supported
  • This system can easily interface to compliant 5G L1 software stack and associated test environments
  • The SmartNIC performance can be extended by further utilizing the PCI Gen3 x16 to full capacity by applying further L1 LDPC or Polar channel coding onto the ZU19EG if fronthaul acceleration is not required
  • This system has been designed to provide optimal throughput and reduced latency for real world scenarios

SD-FEC decoder

AccelerComm has also partnered with Xilinx to deliver all the code block chain components required to support 3GPP TS38.212 around the hardened SD-FEC LDPC decoder available with Zynq® UltraScale+™ RFSoC devices from Xilinx.  It implements the entire LDPC encoding and decoding chain with superior performance and hardware efficiency. 

Technical resources

Our technical resources are freely available for anyone to download. Research and innovation form an integral part of our business and we want to share this with you.

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Datasheets

Detailed specification sheets for our LDPC product, including block diagrams, performance graphs and comparison tables.

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Whitepapers

Research, technical leadership and tutorial papers from our CTO on the latest factors influencing the future of LDPC standards.

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Software

Open source software models and evaluation code for encoder and decoder simulations for our LDPC product.

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AccelerComm intro presentation

Delivering 5G communications

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LDPC product overview

5G NR LDPC Product Overview

Key features and benefits of our LDPC product suite for 5G New Radio Applications.

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