5G NR Complete High PHY

As the wireless telecommunication industry evolves to becoming open, virtualized and disaggregated, there is an increased need for interoperable solutions to cater for the expanding ecosystem. As a result, AccelerComm is developing complete 5G NR High PHY implementations for Split 6 RU and Split 7 DU. Pre-integrated with AccelerComm's LDPC, Polar, PUSCH decoder and PDSCH encoder channels, this complete solution in line with 3GPP standards and O-RAN, SCF specifications, results in maximum performance and efficiency.

The high-level block diagram below shows the various functions of the Split 6 RU High PHY solution.

PxSCH product icon


Integrating and validating the various functional blocks of the 3GPP Physical Layer consumes significant engineering resource and by providing a complete pre integrated IP solution, AccelerComm simplifies the design of a high performance gNB. For instance, a key bottleneck in the Uplink receive chain is often the very high data rate required to pass data to the LDPC decoder as LLRs. By integrating the Demodulator and LDPC Decoder and passing the data as IQ values, the AccelerComm IP offers an opportunity to reduce this bottleneck by a factor of two.

  • Implemented for 3GPP NR specifications and compliant with TS 38.211 and 38.212
  • New QAM modulator/demodulator functionality complements existing LDPC and Polar coding solutions
  • Inherits all the benefits from the existing AccelerComm LDPC, Polar encoders/decoders
  • Support for Uplink Control information (UCI) multiplexed onto the PUSCH
  • Improved BLER for UCI control data
  • Configurable to different parallelisms specific to each integration
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By focussing on 5G NR, we have created an innovative LDPC solution that provides the best of block-parallel and row-parallel architectures, resulting in maximum performance and efficiency. This innovative design combined with configurability enables flexible LDPC decoders with high throughput, low latency, and high hardware efficiency without introducing error floors for high throughput communication systems.

  • Proven in IEEE standards, selected for data channel in 5G NR
  • Complete 3GPP compliant chain
  • 16x latency improvement (to support numerology 4)
  • Supports full code block and transport block processing
  • Open standard software API’s (DPDK) and reference kits
  • Delivered in multiple form factors for ASIC, FPGA and Software only
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This relatively new code base, selected by the 3GPP for 5G NR, is incredibly complex. We have created a unique Polar architecture which enables higher degrees of parallel processing than before. It is easy to integrate, significantly reducing resource and memory usage while delivering excellent BLER performance. 

  • Selected for 5G NR control channel
  • Patented IP, complete 3GPP compliant chain
  • High degrees of parallel processing and scalability
  • Superior hardware efficiency and latency reduction
  • Delivered in multiple form factors for ASIC, FPGA and Software only
  • Configurable decoder list size to best fit the BLER/PPA requirements
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The AccelerCommTM Turbo decoder is a unique patented implementation to enable a highly parallel architecture that’s required to meet the performance and low latency demands of next-generation wireless communication systems.  

  • Proven in 4G, will be used in 3GPP LTE pro & NB-IoT
  • Compliant with 3GPP rel 8 – 15
  • 10X improvements tin information throughput speeds and latency reduction
  • Delivered in multiple form factors for ASIC and FPGA
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Compare products

  LDPC code Polar code Turbo Code
Maturity Proven in IEEE standards, selected for data channel in 5G NR Selected for 5G NR control channel Proven in 3G & 4G, will be used in 3GPP rel 14 & NB-IoT
Flexibility Achievable with the AccelerCommTM approach Achievable with the AccelerCommTM approach Very flexible frame length and coding rate
Computational complexity Lower for most coding rates Lower for most coding rates Higher for most coding rates
Interconnect complexity Higher Lower Lower
Throughput latency Proven for fully-parallel Proven by AccelerCommTM Proven by AccelerCommTM
Flexible high-throughput implementation complexity Higher, particularly at low coding rates Achievable with the AccelerCommTM approach Lower, particularly at low coding rates
Synergy with 3G & 4G No No Yes


AccelerComm is providing us with Acceleration IP on our Telco Accelerator cards. They are an excellent partner. The one thing I can tell you about AccelerComm, is the high quality of their products. The out of the box experience has always been superb.

Very professionally done, very professional team, easy to work with. They’re great partners.

Raghu M Rao, Director - Wired and Wireless Communications Group AMD

AccelerComm has been a key partner in providing that flexibility in order to meet the performance requirements we need for our customers.

The relationship has been excellent. Because of the nature of our business, where we customise our solutions very specifically for our customers, there’s been a lot of engineering back and forth between ourselves and Accelrcomm. And so quite often, we will need to tailor both their and our solutions to the specific requirements of a given customer.

Paul Sutton, CEO - Software Radio Systems

AccerlerComm is a great partner of ours. We deliver together the IP for the FPGAs. They deliver, they support us and create for us opportunities in the market.

We love Rob. B. He is supporting us with both opportunities and technologically. So a great experience and great company to work with.

Oren Benisty, EVP Strategic Sales - Silicom