AccelerComm's Polar IP delivers the complete 3GPP-compliant encoding and decoding chain for 5G NR control channels. Its unique architecture enables higher degrees of parallel processing than conventional Polar implementations, significantly reducing resource and memory usage while delivering excellent BLER performance across PUCCH, PUSCH, PDCCH and PBCH.
The Polar core uses PC- and CRC-aided Successive Cancellation List decoding to achieve compromise-free error correction performance. Parallelism, latency, throughput and decoder list size are all configurable at synthesis time - including reducing list size below the standard list 8 - giving programme teams precise control over the power and performance trade-off for each target application.
Every component of the encoding and decoding chain is tightly integrated, reducing silicon area and latency without adding integration complexity. The interface is deliberately minimal: only the number of uncoded bits and encoded bits are required as inputs alongside the data. Standard AXI interfaces, MATLAB and C models, and FPGA and ASIC-optimised implementations mean the path from evaluation to production is as short as it can be.