AccelerComm's LDPC IP cores deliver flight-proven FEC performance for 5G and 6G NTN PHY designs. Built on advanced decoding algorithms developed from decades of academic research at the University of Southampton, they provide the error-correction performance that demanding satellite and terrestrial PHY workloads require.
AccelerComm LDPC provides licensable, 3GPP-compliant encoder and decoder IP cores optimised for terrestrial, transparent NTN, and regenerative satellite PHY architectures. Its high-throughput, low-latency design is FPGA- and ASIC-ready, with area-efficient implementations suited to SWaP-constrained satellite payloads and high-density ground infrastructure alike.
Already deployed in orbit on more than 200 commercial satellites, AccelerComm's LDPC IP brings a level of flight heritage that few physical layer vendors can offer. For programme teams designing 5G or 6G NTN systems where link efficiency and error-floor performance are critical, it provides a standards-based foundation that de-risks PHY development from the outset.