3GPP Compliant Chains

Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy integration and minimize the amount of extra work needed.

The polar core uses PC- and CRC-aided SCL polar decoding techniques, in order to achieve compromise-free error correction performance. Our decoding IP has several parameters, which can be adjusted at synthesis-time to scale the parallelism, latency and throughput. The decoder list size can be reduced from the typical list 8, in order to best fit the required application.

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How can we help?


  • Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. Supports the full range of uncoded and encoded block sizes
  • Implements the entire Polar encoding and decoding chain in 3GPP TS38.212
  • High error correction performance from Polar PC/CRC-aided decoder core
  • Tightly integrates the components in the chain to reduce area usage and latency
  • Simple interface, quick to integrate.only the number of uncoded bits (A) and encoded bits (E) needs to be input alongside the bits or LLRs
  • FPGA support for Xilinx, Intel and Achronix
  • Optimized for ASIC process
  • Optimized software solution on Intel Architecture and AVX512 acceleration
  • Matlab and C Models available
  • Configurable parameters for power and performance optimization
  • Scalable design with configurable list size
  • Standard AXI interfaces

Solving the Memory Usage problem

In this short video, our CTO Rob Maunder explains what Polar Codes are, and what sets AccelerComm's solution apart from the competition.

Competitor Comparison

Polar encoder & decoder core features AccelerComm  Competitors 
Compliant with 3GPP NR PUCCH, PUSCH, PBCH, PDCCH Yes Yes
CRC calculation, CRC scrambling, CRC interleaving, decoder early termination Included Included
Bit allocation generator, code block segmentation, sub-block interleaving, rate matching bit selection, channel interleaving, code block concatenation Included Not included
Parallelism Synthesis-time configurable Fixed
Interface AXI4-Stream AXI4-Stream
Decoder algorithm CRC-aided SCL SCL
Decoder list size Synthesis-time configurable between L = 1, 2, 4, 8, 16 Fixed to L = 8
Decoder BLER performance @ L=8 Near optimal 1 dB worse in many cases
Decoder core FPGA resourceusage @ L= 8 15 kLUTs 51 kLUTs
Decoder core latency @ L=8, K=200, N=1024 9 us 18 us
Decoder core hardware efficiency @ L=8, K=200, N=1024 1.7 Mbps/kLUT 1.7 Mbps/kLUT
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Functional specifics

Encoder Decoder
CRC aided SCL encoding CRC aided SCL decoding
Zero padding Sub block de-interleaving
CRC24C attachment Filler bits insertion/removal
CRC scrambling and interleaving Rate dematching
Frozen bit insertion Channel de-interleaver
Sub block interleaving  
Rate matching  

Technical resources

Our technical resources are freely available for anyone to download. Research and innovation form an integral part of our business and we want to share this with you.



Detailed specification sheets for our Polar product, including bloc diagrams, performance graphs and comparison tables.

View Datasheets


Research, technical leadership and tutorial papers from our CTO on the latest factors influencing the future of Polar standards.

View Whitepapers


Open source software models and evaluation code for encoder and decoder simulations across our Polar product.

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We are transforming the next generations of wireless communications with innovative, world-leading IP that delivers ultra-high performance and error resilient signal processing. Let’s connect to discuss how our channel coding solutions can help your business thrive today and into the future.

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