Software Acceleration for FlexRan
Intel’s FlexRAN reference platform is widely used within the industry. For smaller base station deployments FlexRAN provides a complete software only solution. The novel AccelerComm LDPC decoding algorithms are available as a software only component, which is a direct replacement for the standard decoders provided with FlexRAN and achieves a three-fold throughput increase leading to greater capacity or reduced cost and power consumption.
Increase your throughput
AccelerComm have developed highly optimized LDPC & Polar software decoders in collaboration with Intel. The solution is integrated into the Intel’s FlexRAN Reference Software resulting in increased throughput by up to 3 times over alternate LDPC implementations and 3.5 times for Polar. These decoders benefit from a combination of optimized architectural and algorithmic enhancements and use of the powerful Intel Architecture and Intel Advanced Vector Instructions 512 (Intel AVX512) instruction sets.
The installer is designed to provide quick and easy integration into FlexRAN and minimize the amount of extra work needed. AccelerComm are also supporting extensions to DPDK & BBDEV to continuously drive down integration time. Both cores are designed with advanced architectures to achieve compromise-free error correction performance with high hardware efficiency.
FlexRAN LDPC software decoder
LDPC software features
- Fully compliant with the 3GPP New Radio standard for PDSCH, PUSCH
Supports the full range of uncoded and encoded block sizes
Implements the LDPC decoding core in 3GPP TS38.212
High error correction performance
Simple interface, quick to integrate – all parameters are internally calculated
FlexRAN LDPC Databrief
Comparison between LDPC decoder from FlexRAN SDK version 19.10.02 and AccelerComm LDPC decoder r1p0, both running on Intel® Xeon 6148 Gold at 2.2 GHz using CentOS Linux 7 (Core) and Intel C Compiler version 18.104.22.168 (GCC version 4.8.5 compatibility):
- BLER performance of decoders is within 0.1 dB of each other – AccelerComm LDPC decoder is superior in BG2 at long block lengths
- AccelerComm LDPC decoder is up to 2.6 times faster – longer block lengths and lower coding rates give higher speedups
- AccelerComm LDPC decoder r1p0 has a configurable tradeoff between BLER performance and throughput – mode 3 is default
Polar software decoder
Polar software features
- The polar core uses PC- and CRC-aided SCL polar decoding techniques with additional algorithmic optimization and pipelining
- Fully compliant with the 3GPP NR standard for PUCCH, PUSCH, PDCCH and PBCH. No limitations on uncoded or encoded block size
- Implements decoding core in 3GPP TS38.212
- High error correction performance
- Simple interface, quick to integrate – all parameters are internally calculated
PUCCH Polar Databrief
Run on an Intel® Skylake® i7-7800X CPU at 3.50 GHz. The BLER performance of our PUCCH decoding IP is within 0.1 dB of that achievable using floating-point min-sum decoding, for all combinations of information block length A and core block length N.
- Compared to the Intel SCL decoder core, our decoding IP offers superior BLER performance for all combinations of information block length - with gains of up to 0.5 dB at short information block lengths
- The processing time of our CRC-aided SCL decoder core is consistently around 3.5 times lower than that of the Intel SCL decoder core, for all combinations of information block length