In this video Professor Rob Maunder discusses AccelerComm's LDPC codes.
AccelerComm's LDPC channel code is a 3rd of the size of it's competition providing high performance low power 5G NR solutions in FPGA and ASIC. This is a fully compliant 3GPP chain including rate matching, HARQ, interleaving etc.
Hello, i’m Rob Maunder, i’m the CTO of AccelerComm and i’d like to tell you all about LDPC codes.
So LDPC is used for error correction in 5g new radio. Some providers of IP for LDPC decoding have taken their previous implementations from wifi and DVB and they’ve tweaked them and they've adjusted them to meet the requirements, the specification for 5G new radio, but this has meant that they haven’t been able to exploit the very particular structure that the LDPC and LDGM concatenation gives.
So the approach that Accelercomm has taken is in contrast to this. We’ve started from scratch with a new architecture and a new algorithm specifically designed for 3GPP LDPC code. This brings us very significant advantages in terms of hardware efficiency. Our hardware efficiency is double that of other solutions that are available, thanks to our novel innovations
We’re here at mobile world congress demonstrating our IP which we’re running here on an arria 10 FGPA board. We have a graphical user interface quantifying the error correction performance that we can achieve using this architecture in real time.
Our IP is available for both FPGA and ASIC and we’re implementing not just the LDPC core, but all of the chain components that go with it, including CRC rate matching hybrid ARQ.
This is really important because other suppliers are providing only the core and have a complicated interface that requires you to segment your inputs into inconveniently sized partitions.
So please get in touch if we can help you with LDPC and if you’d like to receive any datasheets from us.